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Our Memory Offering

    The growth in computationally intensive applications is driving the need for low-power design solutions. Running complex computations, as required by image/speech processing, and machine learning come at a significant cost to the power consumption is a key challenge with battery operated devices.

    Historically, the unit that performs the computations, referred to as processor has consumed the dominant share of power, and had a larger silicon footprint than memory. However, with advances in transistor technologies, according to Moore’s law, and an increased demand for data hungry operations, the memory has gradually become dominant. In todays’ s SoCs (System on Chips)[1], memory may consume up to 80 % of the power budget and 70 % of the area.

    The most efficient approach towards increasing battery life by improving power efficiency is to operate the system at a scaled supply voltage. This is attractive as the operating voltage has linear and quadratic dependence on standby and active power, respectively. This approach comes however with a few key challenges. First is related to performance. Memories show a higher access frequency drop than the logic, therefore they become a major bottleneck for maintaining high system operating frequency. Second consists in the difficulty to find a sufficiently low voltage SRAM at all since, particularly in new technologies, due to process variations the memory bitcell stability is limited and does not scale well far below nominal operating voltage. Third is related to one solution to this problem which is using dual rail memories where the bitcell arrays are kept at nominal voltage. This is a standard industrial approach which requires an additional power domain for the bitcells, usually leveraged using DC-DC converters in battery powered systems. Having bitcells operating at higher voltages comes with the cost of higher static power and DC-DC converter and implementing the additional voltage domain may expose the smaller SoCs to a higher area and power overhead. Moreover, in the case of having the core and memories in different voltage domains, the use of level shifters would be required which can also lead to an additional power and area penalty.

    Yet another challenge for emerging markets (in particular in the domain of IoT, sensors, smart devices, etc.) where power is critical but performance constraints are relaxed, is the potential lack of fitting memory products for the given application. Most memory IP vendors provide a number of different compilers highly optimized for performance with some degrees of optimization for power and leakage, mostly by reusing faster or slower transistors and bitcells and some tweaks in the architecture. In consequence for applications where the performance is relaxed it might be impossible for customers to find a product matching their requirements and they are forced to “pay” in leakage or access energy for a performance they do not need.



    Xenergic’s memory solution

    Xenergic approach consists in providing single rail memories tightly coupled with the customer requirement for any given application in respect to power (both static and dynamic), performance and area. Our methodology allows us to push the boundaries beyond what is currently available in the market in terms of operating voltage and power efficiency with comparable area cost. In order to achieve this, we have developed the MemoryTailorTM, an all-in-one in-house smart memory compiler. It enables us to deliver application-tailored memories to customers based on our power-efficient architectures with short time-to-market even if an adaptation of a new technology is required. 

    Xenergic memories are using foundry-provided memory bitcells. We provide standard memory interface with DFT views, facilitating easy integration in the existing design flows on the customer side. Our products support all standard optional memory features like redundancy, ECC, external tuning, periphery power gating, sleep modes, periphery body biasing (if applicable), etc.

    Xenergic memories, due to their power efficiency and supply voltage scaling capabilities, can push the boundaries of minimum system operating voltage and thus, enable new design options not currently available for customers. Figure below shows an example of system level power evaluation of a low voltage commercial processor operating in 100-150MHz frequency range performed by the customer.

    Xenergic’s memory enabled a reliable operation at 650mV which was not possible using memories from other memory IP providers. Comparison of leakage and dynamic power between 800mV and 650mV with Xenergic memory showed a 90% decrease in the former and 70% in the latter.

    Xenergic  MemoryTailorTM


    Xenergic SRAM compiler MemoryTailorTM utilises innovative patented low-power memory architecture and methodology to provide memories that are optimised for customer specification. In order to meet customer specifications and maintain robustness and reliability of the memories, it is imperative to perform stringent analysis of each design component.

    To this end, Xenergic has developed XenVerifier, an integrated high-yield characterization tool within MemoryTailorTM, which accurately evaluates all components of the memory with respect to power, performance and reliability. Key feature of XenVerifier is the ability to rigorously evaluate the bitcell behaviour for 6σ+ yield by using a patented approach for rare failure event simulation. It enables rare failure rate simulation with a speedup of over 6 orders of magnitude compared to conventional industrial approach, see figure below. The method has been verified to accurately find the most likely points of failure in designs with over 300 variation parameters and dynamically modify sampling distributions accordingly.

    The high speed and accuracy of the XenVerifier allows us to evaluate bitcell performance and stability under a wide range of combinations of architecture choices and assist techniques. This information is then fed to XenCompiler which chooses the most efficient configuration that meets the provided specifications. Finally, based on the chosen tailored architecture, the MemoryTailorTM Assembler generates all the required front-end and back-end views for a seamless integration in the customers’ products.


    [1] System on Chip could be a Central Processing Unit (CPU), Graphical Processing Unit (GPU), etc

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